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CXA3256R 8-bit 120msps flash a/d converter description the CXA3256R is an 8-bit high-speed flash a/d converter capable of digitizing analog signals at the maximum rate of 120msps. ecl, pecl or ttl can be selected as the digital input level in accordance with the application. the ttl digital output level allows 1: 2 demultiplexed output. the CXA3256R is easier to be used by adding the new functions to the cxa3246q and adopting a ultra-small package. features differential linearity error: 0.5lsb or less integral linearity error: 0.5lsb or less high-speed operation with a maximum conversion rate of 120msps low input capacitance: 10pf wide analog input bandwidth: 250mhz low power consumption: 500mw power saving function 1: 2 demultiplexed output 1/2 frequency-divided clock output (with reset function) compatible with ecl, pecl and ttl digital input levels ttl output "h" levels: 2.8v (typ.) output voltage control function (voclp) +3.3v line cmos ic direct connecting available single +5v power supply operation available ultra-small surface mounting package (48-pin lqfp) pin configuration (top view) structure bipolar silicon monolithic ic applications magnetic recording (prml) communications (qpsk, qam) lcds digital oscilloscopes ?1 e98305b22-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. clk/e select2 clk/t voclp ps dv cc 2 dgnd2 pad0 pad1 pad2 pad3 clkn/e pad4 pad7 pad6 dgnd1 dv cc 1 dv cc 2 dgnd2 pbd0 pbd1 pbd2 pbd3 pad5 resetn/e select1 resetn/t inv clkout dv cc 2 dgnd2 pbd7 pbd6 pbd5 pbd4 reset/e dv ee 3 v rm 1 agnd av cc v in v rm 2 av cc v rm 3 agnd v rt dgnd3 v rb 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 1 48 pin lqfp (plastic) lead treatment: palladium plating
2 CXA3256R absolute maximum ratings (ta = 25 c) unit supply voltage av cc , dv cc 1, dv cc 2 0.5 to +7.0 v dgnd3 0.5 to +7.0 v dv ee 3 7.0 to +0.5 v dgnd3 dv ee 3 0.5 to +7.0 v analog input voltage v in v rt 2.7 to av cc v reference input voltage v rt 2.7 to av cc v v rb v in 2.7 to av cc v |v rt v rb | 2.5 v digital input voltage ecl/pecl input pin dv ee 3 0.5 to dgnd3 + 0.5 v ttl input pin dgnd1 0.5 to dv cc 1 + 0.5 v select2 pin dgnd1 0.5 to dv cc 1 + 0.5 v voclp pin dgnd1 0.5 to dv cc 1 + 0.5 v vid ? 1 (| ??? /e ??? n/e|) 2.7 v storage temperature tstg 65 to +150 c allowable power dissipation p d 1.4 w (when mounted on a two-layer glass fabric base epoxy board with dimentions of 50mm 50mm, 1.6mm thick) recommended operating conditions with a single power supply with dual power supply unit min. typ. max. min. typ. max. supply voltage dv cc 1, dv cc 2, av cc +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 v dgnd1, dgnd2, agnd 0.05 0 +0.05 0.05 0 +0.05 v dgnd3 +4.75 +5.0 +5.25 0.05 0 +0.05 v dv ee 3 0.05 0 +0.05 5.5 5.0 4.75 v analog input voltage v in v rb v rt v rb v rt v reference input voltage v rt +2.9 +4.1 +2.9 +4.1 v v rb +1.4 +2.6 +1.4 +2.6 v |v rt v rb | 1.5 2.1 1.5 2.1 v digital input voltage ecl/pecl input pin : v ih dv ee 3 + 1.5 dgnd3 dv ee 3 + 1.5 dgnd3 v : v il dv ee 3 + 1.1 v ih 0.4 dv ee 3 + 1.1 v ih 0.4 v ttl input pin : v ih 2.0 2.0 v : v il 0.8 0.8 v select2 pin : v ih dv cc 1dv cc 1v : v il dgnd1 dgnd1 v voclp pin dgnd1 + 2.4 dv cc 1 dgnd1 + 2.4 dv cc 1 v vid ? 1 (| ??? /e ??? n/e|) 0.4 0.8 0.4 0.8 v maximum conversion rate fc (straight mode) 100 100 msps (dmux mode) 120 120 msps ambient temperature ta 20 +75 20 +75 c ? 1 vid: input voltage differential ecl and pecl switching level vid v il (min.) v ih v th (dgnd3 1.2v) v il v ih (max.) dgnd3
3 CXA3256R pin description [symbol] [pin no.] [description] digital power supply bottom reference voltage analog ground reference voltage mid point analog power supply analog signal input reference voltage mid point analog power supply reference voltage mid point analog ground reference voltage (typ.) digital power supply ecl/pecl clock input ecl/pecl clock input ttl clock input data output switching ttl high level clamp power saving digital power supply digital ground pa side data output digital ground digital power supply digital power supply digital ground pb side data output digital ground digital power supply clock output data output polarity inversion output mode selection ttl reset input ecl/pecl reset input ecl/pecl reset input 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 to 28 29 30 31 32 33 to 40 41 42 43 44 45 46 47 48 dv ee 3 v rb agnd v rm 1 av cc v in v rm 2 av cc v rm 3 agnd v rt dgnd3 clk/e clkn/e clk/t select2 voclp ps dv cc 2 dgnd2 pad0 to pad7 dgnd1 dv cc 1 dv cc 2 dgnd2 pbd0 to pbd7 dgnd2 dv cc 2 clkout inv select1 resetn/t reset/e resetn/e 0v 1.4 to 2.6v 0v +5v v rb to v rt +5v 0v 2.9 to 4.1v +5v pecl pecl ttl dgnd1 or open or dvcc1 clamp voltage ttl +5v 0v ttl 0v +5v +5v 0v ttl 0v +5v ttl ttl ttl ttl pecl pecl 5.0v 1.4 to 2.6v 0v +5v v rb to v rt +5v 0v 2.9 to 4.1v 0v ecl ecl ttl dgnd1 or open or dvcc1 clamp voltage ttl +5v 0v ttl 0v +5v +5v 0v ttl 0v +5v ttl ttl ttl ttl ecl ecl typical voltage level with a single power supply typical voltage level with dual power supply
4 CXA3256R block diagram 6bit v rt 2 3 5 8 10 12 13 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 44 1 1 2 r /2 63 64 65 126 127 128 129 191 192 193 254 255 r 6bit 9 7 4 r 1 r 2 r r r r r r r r r r r r r r /2 6bit 6bit 8bit 8bit 15 46 47 48 select dq q 45 select1 11 43 dgnd1 dv ee 3 dgnd2 agnd av cc dv cc 2 dv cc 1 inv dgnd3 vrm3 v in vrm2 6 v rb vrm1 clk/t clk/e clkn/e resetn/t resetn/e reset/e clkout pad0 pad1 pad2 pad3 pad4 pad5 pad6 pad7 pbd0 pbd1 pbd2 pbd3 pbd4 pbd5 pbd6 pbd7 ttlout latch a ttlout latch b 6bit latch + encoder encoder (lsb) (msb) (lsb) (msb) latch b select2 voclp ps
5 CXA3256R pin description and i/o pin equivalent circuit analog ground. separated from the digital ground. analog power supply. separated from the digital power supply. digital ground. digital power supply. digital power supply. ground for ecl input. +5v for pecl and ttl inputs. digital power supply. 5v for ecl input. ground for pecl and ttl inputs. data output switching. data is output from both the pa side and pb side by setting this pin open. when set to dvcc1 level, only the pa side output port outputs the data, makes the pb side high impedance. when set to dgnd1 level, only the pb side output port outputs the data, makes the pa side high impedance. dv cc 1 or open or dgnd1 i select2 16 3, 10 5, 8 20, 29 32, 41 19, 30 31, 42 12 1 agnd av cc dgnd1 dgnd2 dv cc 1 dv cc 2 dgnd3 dv ee 3 gnd +5v (typ.) gnd +5v (typ.) +5v (typ.) (with a single power supply) gnd (with dual power supply) gnd (with a single power supply) 5v (typ.) (with dual power supply) pin no. symbol i/o standard voltage level equivalent circuit description dv cc 1 dgnd1 r 16 r r ttl output high level clamp. the ttl high level voltage is clamped to the approximately same value as the voltage applied to this pin. even if this pin is left open, the ttl high level is clamped to approximately 2.8v. clamp voltage i voclp 17 dv cc 2 dgnd2 17 3k 3.5k
6 CXA3256R pin no. 15 clk/t clock input. 46 resetn/t ttl ttl vcc or gnd reset signal input. when left open, this pin goes to high level. when set to low level, the built-in clk frequency divider circuit can be reset. 44 inv data output polarity inversion input. when left open, this input goes to high level. (see table 1. i/o correspondence table.) 45 select1 data output mode selection. (see table 2. operation mode table.) symbol standard voltage level equivalent circuit description 15 46 dv cc 1 dgnd1 dv ee 3 44 45 or , 1.5v i i i i/o clock input. clk/e complementary input. when left open, this pin goes to the threshold voltage. only clk/e can be used for operation, but complementary inputs are recommended to attain fast and stable operation. reset signal input. when set to low level, the built-in clk frequency divider circuit can be reset. resetn/e complementary input. when left open, this pin goes to the threshold voltage. only resetn/e can be used for operation. ecl/ pecl ttl 13 14 48 47 clk/e clkn/e resetn/e reset/e i power saving. when left open, this pin goes to high level. when set to low level, the power saving state is established. 18 ps i i i i 13 14 48 47 dgnd3 dv ee 3 dv cc 1 dgnd1 18
7 CXA3256R 4.0v (typ.) 11 v rt top reference voltage. by-pass to agnd with a 1f tantal capacitor and a 0.1f chip capacitor. v rb + (v rt v rb ) 9 v rm 3 reference voltage mid point. by-pass to agnd with a 0.1f chip capacitor. 7 v rm 2 reference voltage mid point. by-pass to agnd with a 0.1f chip capacitor. 4 v rm 1 reference voltage mid point. by-pass to agnd with a 0.1f chip capacitor. 2.0v (typ.) 2 v rb bottom reference voltage. by-pass to agnd with a 1f tantal capacitor and a 0.1f chip capacitor. r 1 r /2 comparator 1 comparator 63 comparator 64 comparator 128 comparator 191 comparator 127 comparator 192 comparator 255 r r 2 r /2 r r r r 4 7 9 2 11 r i i 4 3 4 2 v rb + (v rt v rb ) 4 1 v rb + (v rt v rb ) pin no. symbol i/o standard voltage level equivalent circuit description clock output. (see table 2. operation mode table.) ttl output; the high level is clamped to approximately 2.8v. 21 to 28 pad0 to pad7 port a side data output. ttl output; the high level is clamped to approximately 2.8v. 33 to 40 pbd0 to pbd7 43 clkout port b side data output. ttl output; the high level is clamped to approximately 2.8v. 6v in v rt to v rb i ttl o o o analog input. av cc comparator vref agnd dv ee 3 av cc 6 dv cc 2 dgnd2 dv cc 1 dgnd1 100k d vee 3 21 28 33 40 43 to to
8 CXA3256R resolution dc characteristics integral linearity error differential linearity error analog input analog input capacitance analog input resistance analog input current reference input reference resistance reference current offset voltage v rt side v rb side digital input (ecl, pecl) digital input voltage: high : low threshold voltage digital input current : high : low digital input capacitance digital input (ttl) digital input voltage: high : low threshold voltage digital input current : high : low digital input capacitance digital output (ttl) digital output voltage : high : low switching characteristics maximum conversion rate aperture jitter sampling delay clock high pulse width clock low pulse width reset signal setup time reset signal hold time clock output delay data output delay output rise time output fall time electrical characteristics (av cc , dv cc 1, 2, dgnd3 = +5v, agnd, dgnd1, 2, dv ee 3 = 0v, v rt = 4v, v rb = 2v, ta = 25 c) item symbol min. typ. max. unit conditions e il e dl c in r in i in rref ? 2 iref ? 3 eot eob v ih v il v th i ih i il v ih v il v th i ih i il v oh v ol fc taj tds tpw1 tpw0 t_rs t_rh td_clk tdo1 tdo2 tr tf 7 0 400 2.7 6 0 dv ee 3 + 1.5 dv ee 3 + 1.1 50 50 2.0 10 20 2.4 120 1.2 3.0 4.5 1.0 0.5 3.0 3.5 8 10 20 100 600 3.3 8 1.5 dgnd3 1.2 1.5 10 1.4 4.5 t ? 4 + 0.5 5.0 1 1 0.5 0.5 40 285 740 5.0 10 3 dgnd3 v ih 0.4 20 20 5 0.8 5 0 5 0.5 1.6 7.0 7.5 bits lsb lsb pf k ? a ? ma mv mv v v v a a pf v v v a a pf v v msps ps ns ns ns ns ns ns ns ns ns ns v in = 2vp-p, fc = 5msps v in = +3.0v + 0.07vrms v ih = dgnd3 0.8v v il = dgnd3 1.6v v ih = 3.5v v il = 0.2v i oh = 2ma i ol = 1ma dmux mode clk clk resetn clk resetn clk (c l = 5pf) dmux mode (c l = 5pf) (c l = 5pf) 0.8 to 2.0v (c l = 5pf) 0.8 to 2.0v (c l = 5pf) ? these characteristics are for pecl input unless otherwise specified.
9 CXA3256R ? 4 t = ? 5 tps: times per sample ? 6 pd = (i cc + i ee ) v cc + ? 7 pd = (i cc + i ee ) v cc (v rt v rb ) 2 rref dynamic characteristics input bandwidth snr error rate power supply supply current avcc pin supply current dvcc1 pin supply current dvcc2 pin supply current dgnd3 pin supply current supply current for ps avcc pin supply current for ps dvcc1 pin supply current for ps dvcc2 pin supply current for ps dgnd3 pin supply current for ps power consumption power consumption for ps i cc + i ee ai cc di cc 1 di cc 2 i ee i cc +i ee ai cc di cc 1 di cc 2 i ee pd ? 6 pd ? 7 250 70 45 20 5 0.5 400 0.3 46 42 98 500 10 12 10 9 10 9 140 87 36 15 1.5 5 1.5 1.5 1.5 0.5 700 25 mhz db db tps ? 5 tps tps ma ma ma ma ma ma ma ma ma ma mw mw v in = 2vp-p, 3db fc = 120msps, fin = 1khz fs dmux mode fc = 120msps, fin = 29.999mhz fs dmux mode fc = 120msps, fin = 1khz fs dmux mode error > 16lsb fc = 120msps, fin = 29.999mhz fs dmux mode error > 16lsb fc = 100msps, fin = 24.999mhz fs straight mode error > 16lsb { { { { { 1 fc item symbol min. typ. max. unit conditions ? 2 rref: resistance value between v rt and v rb ? 3 iref = v rt v rb rref
10 CXA3256R table 1. i/o correspondence table inv 1 d7 d0 d7 d0 0 v in v rt v rm 2 v rb 255 254 . . . 128 127 . . . 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 . . . 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 . . . 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 . . . 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 step
11 CXA3256R electrical characteristics measurement circuit current consumption measurement circuit v rt v in v rb av cc dv cc 1 dv cc 2 ps dgnd3 dgnd2 dgnd1 agnd clk/e dv ee 3 5mhz pecl 4v 1.95v 2v 5v 5v icc i ee integral linearity error measurement circuit differential linearity error measurement circuit CXA3256R a < b a > b comparator a8 to a1 a0 b8 to b1 b0 buffer controller dvm 8 8 1 0 000 00 to 111 10 v in +v v s2 s1 s1: on when a < b s2: on when a > b sampling delay measurement circuit aperture jitter measurement circuit CXA3256R osc1 : variable osc2 logic analizer 100mhz 100mhz amp ecl buffer clk v in 8 fr 1024 samples aperture jitter measurement method v in clk v in clk v rt v rm 2 v rb 129 128 127 126 125 sampling timing fluctuation (= aperture jitter) (lsb) ? ? t error rate measurement circuit comparator a > b pulse counter CXA3256R signal source latch latch 1/8 + signal source fc 4 1khz 2vp-p sine wave fc v in clk clk 8 16lsb a b where (lsb) is the deviation of the output codes when the largest slew rate point is sampled at the clock which has exactly the same frequency as the analog input signal, the aperture jitter taj is: taj = / = / ( ) ? t ? 2 256 2 f
12 CXA3256R description of operation modes the CXA3256R has two types of operation modes which are selected with pin 45 (select). 1. dmux mode (see application circuit 1-(1), (2) and (3).) set the select1 pin to vcc for this mode. in this mode, the clock frequency is divided by 2 in the ic, and the data is output after being demultiplexed by this 1/2 frequency-divided clock. the 1/2 frequency-divided clock, which has adequate setup time and hold time for the output data, is output from the clock output pin. when using the multiple CXA3256R in dmux mode, the start timing of the 1/2 frequency-divided clocks becomes out of phase, producing operation such as that shown in the example on the next page. as a countermeasure, the CXA3256R has a function that resets the 1/2 frequency-divided clocks. when resetting this 1/2 frequency-divided clock, the low level of the reset signal should be input to the resetn pin (pin 46 or 48). the reset signal requires the setup time (t_rs 1.0ns) and hold time (t_rh 0.5ns) to the clock rising edge because it is synchronized with and taken in the clock. the reset period can be extended by making the low level period of the reset signal longer because the clock output pin is fixed to low (reset) during the low level period at the clock rising edge. if the reset start timing is regarded as not important, the timing where the reset signal is set from high to low is not so consequence. however, when the reset is released the timing where the reset signal is set from low to high must become significant because the timing is used to commence the 1/2 frequency-divided clock. in this case, the setup time (t_rs) is also necessary. see the timing chart for detail. (this chart shows the example of reset for 2t.) the a/d converter can operate at fc (min.) = 120msps in this mode. table 2. operation mode table select1 pin v cc gnd dmux mode straight mode 120msps 100msps demultiplexed output 60mbps straight output 100mbps the input clock is 1/2 frequency divided and output. 60mhz the input clock is inverted and output. 100mhz operation mode maximum conversion rate data output clock output
13 CXA3256R 8bit clkout data 8bit clkout data clk a b clk aaa a a a aaa aaa aaa CXA3256R CXA3256R clk resetn clk resetn a b aaa a a a aaa aaa aaa 8bit clkout data 8bit clkout data clk CXA3256R CXA3256R a b clk resetn clk resetn clk reset signal reset signal (reset period) (reset period) 2. straight mode (see application circuits 1-(4), (5) and (6).) set the select1 pin to gnd for this mode. in this mode, data output can be obtained in accordance with the clock frequency applied to the a/d converter for applications which use the clock applied to the a/d converter as the system clock. the a/d converter can operate at fc (min.) = 100msps in this mode. digital input level and supply voltage settings the logic input level for the CXA3256R supports ecl, pecl and ttl levels. the power supplies (dv ee 3, dgnd3) for the logic input block must be set to match the logic input (clk and reset signals) level. digital input level ecl pecl ttl 5v 0v 0v 0v +5v +5v 5v +5v +5v (1) (4) (2) (5) (3) (6) dv ee 3 dgnd3 supply voltage application circuits table 3. logic input level and power supply settings when the reset signal is not used when the reset signal is used select2 pin open vcc1 gnd1 output possible to both pa and pb output possible to pa, and pb output is high impedance. output possible to pb, and pa output is high impedance. data output description of select2 pin the CXA3256R has the two systems of data output. the select2 pin is used to select the port where the data is output.
14 CXA3256R application circuit 1 (1) dmux ecl input +5v(d) dg 5v(d) ag dg +5v(a) 4v +5v(d) dg 8 bit digital data latch 8 bit digital data latch pbd0 to pbd7 8 bit digital data pad0 to pad7 8 bit digital data ecl reset signal ecl-clk dg 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 dg +5v(d) 2v +5v(a) 2 ag ag ag ag (2) dmux pecl input +5v(d) dg +5v(d) dg 8 bit digital data latch 8 bit digital data latch pbd0 to pbd7 8 bit digital data pad0 to pad7 8 bit digital data pecl-clk dg 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 dg +5v(d) 2 +5v(d) ag dg +5v(a) 4v 2v +5v(a) ag ag ag ag pecl reset signal 12 (3) dmux ttl input +5v(d) dg ag ag +5v(a) 4v +5v(d) dg 8 bit digital data latch 8 bit digital data latch pbd0 to pbd7 8 bit digital data pad0 to pad7 8 bit digital data ttl reset signal ttl-clk dg 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 dg +5v(d) 2v ag +5v(a) 2 +5v(d) dg ag ag 12
15 CXA3256R (4) straight ecl input +5v(d) dg +5v(d) dg 8 bit digital data latch pbd0 to pbd7 8 bit digital data ecl-clk dg 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 46 47 48 1 dg +5v(d) 2 ecl ttl dg 45 ag ag +5v(a) 4v 2v ag +5v(a) 5v(d) dg ag ag dg (5) straight pecl input +5v(d) dg +5v(d) dg 8 bit digital data latch pbd0 to pbd7 8 bit digital data pecl-clk dg 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 46 47 48 1 dg +5v(d) 2 pecl ttl dg 45 ag ag +5v(a) 4v 2v ag +5v(a) +5v(d) dg ag ag dg (6) straight ttl input +5v(d) dg +5v(d) dg 8 bit digital data latch pad0 to pad7 8 bit digital data ttl-clk dg 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 46 47 48 1 dg +5v(d) 2 dg 45 ag ag +5v(a) 4v 2v ag +5v(a) +5v(d) dg ag ag +5v(d)
16 CXA3256R application circuit 2 dmux mode ttl i/o (when a single power supply is used) clk/e select2 clk/t voclp ps dv cc 2 dgnd2 pad0 pad1 pad2 pad3 clkn/e resetn/e select1 resetn/t inv clkout dv cc 2 dgnd2 pbd7 pbd6 pbd5 pbd4 reset/e dv ee 3 v rm 1 agnd av cc v in v rm 2 av cc v rm 3 agnd v rt dgnd3 v rb pad4 pad7 pad6 dv cc 1 dv cc 2 dgnd2 pbd0 pbd1 pbd2 pbd3 pad5 dgnd1 a a analog input ag +5v (a) 2v 4v ttl clk (lsb) pad0 pad1 pad2 pad3 pad4 pad5 pad6 (msb) pad7 (lsb) pbd0 (msb) pbd7 pbd1 pbd2 pbd3 pbd4 pbd5 pbd6 1f 10f 10f 1f 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 1 ag ag dg +5v (d) ag ag 24 short short short the analog system and digital system at one point immediately under the a/d converter. see the notes on operation. is the chip capacitor of 0.1f. also, c ? is important to suppress the noise generated during the ttl output circuit is operating. place c ? at the fixed position between the pins with the shortest distance. clamp voltage c ? c ? c ? application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
17 CXA3256R dmux mode timing chart (select = v cc ) clk v in t tpw0 tpw1 n + 2 n + 3 n + 1 n + 4 n +5 n n + 6 tds 1.4ns (typ.) n 1 n 2 2.0v 0.8v n + 1 2.0v 0.8v tdo1 t t pbd0 to d7 pad0 to d7 n n + 2 n + 3 clk out resetn t_rs t_rh t_rs t_rh aa 2.0v aa aa 0.8v (reset period) aa 2.0v aa aa 0.8v tdo2; 5.0ns (typ.) td_clk; 4.5ns (typ.) aa 2.0v aa aa 0.8v t + 0.5ns (typ.) 3.5ns (min) 7.5ns (max) 7.0ns (max) 3.0ns (min) (pin 6) (pin 13) (pins 21 to 28) (pins 33 to 40) (pin 43) (pin 48)
18 CXA3256R straight mode timing chart (select = gnd) tds t tpw1 n + 1 n 1 n n + 2 n + 3 clk v in tpw0 1.4ns (typ.) n 2n pbd0 to d7 n + 1 n 1 n 3 2.0v 0.8v pad0 to d7 n 3n 1 n n 2 n 4 2.0v 0.8v clk out (clk is inverted and output.) 2.0v 0.8v td_clk; 4.5ns (typ.) tdo2; 5.0ns (typ.) 7.0ns (max) 3.0ns (min) 3.5ns (min) 7.5ns (max) (pin 6) (pin 13) (pins 21 to 28) (pins 33 to 40) (pin 43)
19 CXA3256R notes on operation the CXA3256R has the pecl and ttl input pins for the clock and reset input pins. when the clock is input in pecl level, inputting the reset signal in pecl level is recommended. also, when the clock is input in ttl level, inputting the reset signal in ttl is recommended. the impedance of the input signal should be properly matched to ensure the CXA3256R's stable operation at the high speed. in the CXA3256R, all the ttl input pins become the high level when left open. the power supply and grounding have a profound influence on converter performance. the power supply and grounding method are particularly important during high-speed operation. general points for caution are as follows. the ground pattern should be as large as possible. it is recommended to make the power supply and ground patterns wider at an inner layer using a multi-layer board. to prevent interference between agnd and dgnd and between avcc and dvcc, make sure the respective patterns are separated. to prevent a dc offset in the power supply pattern, connect the avcc and dvcc lines at one point each via a ferrite-bead filter, etc. shorting the agnd and dgnd patterns in one place immediately under the a/d converter improves a/d converter performance. be sure to turn the analog and digital power supplies on simultaneously. if not simultaneously, the ic does not operate correctly. ground the power supply pins (avcc, dvcc1, dvcc2, dv ee 3) as close to each pin as possible with a 0.1f or larger ceramic chip capacitor. (connect the avcc pin to the agnd pattern and the dvcc1, dvcc2 and dv ee 3 pins to the dgnd pattern.) it is recommended to place the ceramic chip capacitor of 0.1f or more, in particular, between dvcc2 and dgnd2 with the shortest distance. this has the effect to suppress the noise generated when the CXA3256R ttl output circuit operates. the digital output wiring should be as short as possible. if the digital output wiring is long, the wiring capacitance will increase, deteriorating the output slew rate and resulting in reflection to the output waveform since the original output slew rate is quite fast. the analog input pin v in has an input capacitance of approximately 10pf. to drive the a/d converter with the proper frequency response, it is necessary to prevent performance deterioration due to parasitic capacitance or parasitic inductance by using a large capacity drive circuit, keeping wiring as short as possible, and using chip parts for resistors and capacitors, etc. the v rt and v rb pins must have adequate by-pass to protect them from high-frequency noise. by-pass them to agnd with approximately 1f tantal capacitor and 0.1f chip capacitor as short as possible. if the clkn/e pin is not used, by-pass this pin to dgnd with an approximately 0.1f capacitor. at this time, approximately dgnd3 1.2v voltage is generated. however, this is not recommended for use as the threshold voltage v bb because it is too weak.
20 CXA3256R when the digital input level is ecl or pecl level, ??? /e pins should be used and ??? /t pins left open. when the digital input level is ttl, ??? /t pins should be used and ??? /e pins left open. the CXA3256R ttl output high level is clamped to approximately 2.8 v in the ic.this makes it possible to directly interface with the 3.3v system cmos ic. however,the CXA3256R has the voclp pin which is used to clamp the ttl output high level. see the example of representative characteristics for the relationship between the voclp pin and the ttl high level. the cxa3026q has the output pins p1 ?? and p2 ?? . however, in the CXA3256R, these symbols are changed as pa ?? and pb ?? . at this time, the p1 side of the cxa3026q is changed to the pb side for the CXA3256R; the p2 side of the cxa3026q to the pa side for the CXA3256R. the pipeline delay of the CXA3256R is smaller by one clock, compared to that of cxa3026q.
21 CXA3256R current consumption vs. ambient temperature characteristics ta ambient temperature [ c] 25 90 25 75 current consumption [ma] 95 100 105 110 current consumption vs. conversion rate characteristics fc conversion rate [msps] 0 90 60 current consumption [ma] 95 100 105 110 120 dmux mode c l = 5pf fin = 1khz f clk 4 analog input current vs. analog input voltage characteristics analog input voltage [v] 234 analog input current [a] 50 100 0 reference current vs. ambient temperature characteristics ta ambient temperature [ c] 25 2 25 75 reference current [ma] 3 4 v rt = 4v v rb = 2v example of representative characteristics
22 CXA3256R snr vs. input frequency response input frequency [mhz] 1 20 550 snr [db] 30 40 50 30 310 error rate vs. conversion rate characteristics 120 140 160 10 6 10 7 10 8 10 9 10 10 error > 16lsb fin = 1khz f clk 4 maximum conversion rate vs. ambient temperature characteristics ta ambient temperature [ c] 25 130 25 75 fc maximum conversion rate [msps] 150 170 fin = 1khz f clk 4 140 160 fc = 120msps error > 16lsb error rate: 10 9 tps error rate [tps] fc conversion rate [msps] ttl output high level vs. voclp pin voclp pin voltage [v] 0.5 1 35 ttl output high level [v] 2 3 1 ttl high level when voclp is open.
23 CXA3256R package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ?0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 ?0.02 + 0.05 a 1.5 ?0.1 + 0.2 0.1 palladium plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0? to 10? detail a 0.13 m 0.5 s s b detail b : palladium 0.127 0.04 0.18 0.03 sony corporation

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